#define MXL_HRCLS_LINK_RTL_VER  0x3081
#define       ECO_1                                                       0x0700,0,16
#define       ECO_4                                                       0x070C,0,16
#define       ECO_8                                                       0x071C,0,16
#define       CHIP_VERSION                                                0x07DC,0,4
#define       FPGA_LINK_SPECIFY3                                          0x07EC,0,16
#define       GPIO_MODE                                                   0x0828,3,1
#define       MCK_OE                                                      0x082C,0,1
#define       MPEG0_OE                                                    0x0830,0,1
#define       OOB0_OE                                                     0x0830,1,1
#define       MPEG1_OE                                                    0x0834,0,1
#define       OOB1_OE                                                     0x0834,1,1
#define       MPEG2_OE                                                    0x0838,0,1
#define       OOB2_OE                                                     0x0838,1,1
#define       MPEG3_OE                                                    0x083C,0,1
#define       OOB3_OE                                                     0x083C,1,1
#define       MPEG4_OE                                                    0x0840,0,1
#define       OOB4_OE                                                     0x0840,1,1
#define       MPEG5_OE                                                    0x0844,0,1
#define       OOB5_OE                                                     0x0844,1,1
#define       MPEG6_OE                                                    0x0848,0,1
#define       OOB6_OE                                                     0x0848,1,1
#define       MPEG7_OE                                                    0x084C,0,1
#define       OOB7_OE                                                     0x084C,1,1
#define       MPEG8_OE                                                    0x0850,0,1
#define       OOB8_OE                                                     0x0850,1,1
#define       DMD0_CLOCK_X1_EN                                            0x0858,1,1
#define       DMD0_CLOCK_X2_EN                                            0x0858,3,1
#define       DMD0_CLOCK_X4_EN                                            0x0858,4,1
#define       DMD0_MCLK_EN                                                0x0858,5,1
#define       DMD0_MDVAL_GATE_EN                                          0x0858,6,1
#define       DMD0_MDVAL_GATE_EN_INV                                      0x0858,7,1
#define       DMD0_SWAP_IQ                                                0x0858,8,1
#define       DMD1_CLOCK_X1_EN                                            0x085C,1,1
#define       DMD1_CLOCK_X2_EN                                            0x085C,3,1
#define       DMD1_CLOCK_X4_EN                                            0x085C,4,1
#define       DMD1_MCLK_EN                                                0x085C,5,1
#define       DMD1_MDVAL_GATE_EN                                          0x085C,6,1
#define       DMD1_MDVAL_GATE_EN_INV                                      0x085C,7,1
#define       DMD2_MDVAL_GATE_EN                                          0x0860,6,1
#define       DMD2_MDVAL_GATE_EN_INV                                      0x0860,7,1
#define       DMD3_MDVAL_GATE_EN                                          0x0864,6,1
#define       DMD3_MDVAL_GATE_EN_INV                                      0x0864,7,1
#define       DMD4_MDVAL_GATE_EN                                          0x0868,6,1
#define       DMD4_MDVAL_GATE_EN_INV                                      0x0868,7,1
#define       DMD5_MDVAL_GATE_EN                                          0x086C,6,1
#define       DMD5_MDVAL_GATE_EN_INV                                      0x086C,7,1
#define       DMD6_MDVAL_GATE_EN                                          0x0870,6,1
#define       DMD6_MDVAL_GATE_EN_INV                                      0x0870,7,1
#define       DMD7_MDVAL_GATE_EN                                          0x0874,6,1
#define       DMD7_MDVAL_GATE_EN_INV                                      0x0874,7,1
#define       DMD8_MDVAL_GATE_EN                                          0x0878,6,1
#define       DMD8_MDVAL_GATE_EN_INV                                      0x0878,7,1
#define       DMD8_SWAP_IQ                                                0x0878,8,1
#define       PAD_MPEG_CLK_DRV                                            0x0884,0,3
#define       PAD_MPEG_0_SYN_DRV                                          0x0888,0,3
#define       PAD_MPEG_0_DAT_DRV                                          0x0888,4,3
#define       PAD_MPEG_0_VAL_DRV                                          0x0888,8,3
#define       PAD_MPEG_1_SYN_DRV                                          0x088C,0,3
#define       PAD_MPEG_1_DAT_DRV                                          0x088C,4,3
#define       PAD_MPEG_1_VAL_DRV                                          0x088C,8,3
#define       PAD_MPEG_2_SYN_DRV                                          0x0890,0,3
#define       PAD_MPEG_2_DAT_DRV                                          0x0890,4,3
#define       PAD_MPEG_2_VAL_DRV                                          0x0890,8,3
#define       PAD_MPEG_3_SYN_DRV                                          0x0894,0,3
#define       PAD_MPEG_3_DAT_DRV                                          0x0894,4,3
#define       PAD_MPEG_3_VAL_DRV                                          0x0894,8,3
#define       PAD_MPEG_4_SYN_DRV                                          0x0898,0,3
#define       PAD_MPEG_4_DAT_DRV                                          0x0898,4,3
#define       PAD_MPEG_4_VAL_DRV                                          0x0898,8,3
#define       PAD_MPEG_5_SYN_DRV                                          0x089C,0,3
#define       PAD_MPEG_5_DAT_DRV                                          0x089C,4,3
#define       PAD_MPEG_5_VAL_DRV                                          0x089C,8,3
#define       PAD_MPEG_6_SYN_DRV                                          0x08A0,0,3
#define       PAD_MPEG_6_DAT_DRV                                          0x08A0,4,3
#define       PAD_MPEG_6_VAL_DRV                                          0x08A0,8,3
#define       PAD_MPEG_7_SYN_DRV                                          0x08A4,0,3
#define       PAD_MPEG_7_DAT_DRV                                          0x08A4,4,3
#define       PAD_MPEG_7_VAL_DRV                                          0x08A4,8,3
#define       PAD_MPEG_8_SYN_DRV                                          0x08A8,0,3
#define       PAD_MPEG_8_DAT_DRV                                          0x08A8,4,3
#define       PAD_MPEG_8_VAL_DRV                                          0x08A8,8,3
#define       HCLK_SEL                                                    0x08B4,0,1
#define       MCLK_CTRL                                                   0x08B4,8,3
#define       MCLK_CFG_ENA                                                0x08B4,12,1
#define       CLK_ENA_HI                                                  0x08B8,0,8
#define       CLK_ENA_LO                                                  0x08BC,0,16
#define       MCLK_INV                                                    0x08C0,11,1
#define       SERDES_0_TX_RESET                                           0x08C4,0,1
#define       SERDES_0_RX_RESET                                           0x08C4,1,1
#define       SERDES_1_TX_RESET                                           0x08C8,0,1
#define       SERDES_1_RX_RESET                                           0x08C8,1,1
#define       OOB_MPEG_EN                                                 0x08CC,0,1
#define       OOB_CTRL_CLK_INVT                                           0x08CC,1,1
#define       OOB_CTRL_SYNC_INVT                                          0x08CC,2,1
#define       OOB_CTRL_OUTPUT_VALIDINVT                                   0x08CC,3,1
#define       OOB_CTRL_SOFT_RESET                                         0x08CC,4,1
#define       OOB_PN23_CONST_ENABLE                                       0x08CC,5,1
#define       OOB_TS_MODE                                                 0x08CC,6,1
#define       OOB_TS_SYNC_CLK                                             0x08CC,7,1
#define       OOB_FDBK                                                    0x08CC,8,1
#define       OOB_SYNC_LOSS_TYPE                                          0x08CC,9,1
#define       OOB_RS_FREEZ                                                0x08CC,12,1
#define       OOB_RS_CLEAR                                                0x08CC,13,1
#define       DFE_RESET                                                   0x08D8,0,1
#define       GPIO_DIN                                                    0x08E4,0,8
#define       OOB_SYNC_MPEG_RB                                            0x090C,0,1
#define       OOB_PN23ERR_RB                                              0x0910,0,16
#define       OOB_PN23BITCNT_RB_HI                                        0x0914,0,16
#define       OOB_PN23BITCNT_RB_LO                                        0x0918,0,16
#define       OOB_RS_BLKCNT_RB                                            0x0920,0,16
#define       OOB_RS_BLK_ERRS_RB                                          0x0924,0,16
#define       OOB_RS_UNCORRECT_RB                                         0x0928,0,16
#define       OOB_FEC_MODE                                                0x0938,0,1
#define       OOB_2_CLK_ENABLE                                            0x0938,3,1
#define       OOB_2_SOFT_RESET                                            0x0938,4,1
#define       OOB_2_MCLK_INV                                              0x0938,5,1
#define       OOB_2_SYNC_POLARITY                                         0x0938,6,1
#define       OOB_2_SYNC_WIDTH                                            0x0938,7,1
#define       OOB_2_VALID_POLARITY                                        0x0938,8,1
#define       RS_CTR_CLEAR                                                0x093C,14,1
#define       DMD0_QAM_IQ_SWAP                                            0x0940,0,1
#define       DMD1_QAM_IQ_SWAP                                            0x0940,1,1
#define       DMD2_QAM_IQ_SWAP                                            0x0940,2,1
#define       DMD3_QAM_IQ_SWAP                                            0x0940,3,1
#define       DMD4_QAM_IQ_SWAP                                            0x0940,4,1
#define       DMD5_QAM_IQ_SWAP                                            0x0940,5,1
#define       DMD6_QAM_IQ_SWAP                                            0x0940,6,1
#define       DMD7_QAM_IQ_SWAP                                            0x0940,7,1
#define       DMD8_QAM_IQ_SWAP                                            0x0940,8,1
#define       LOCK_SIGNAL_RB                                              0x0944,6,1
#define       RS_TOTAL_PKT_CTR_RB_HI                                      0x0948,0,8
#define       RS_TOTAL_PKT_CTR_RB_LO                                      0x094C,0,16
#define       RS_CORR_PKT_ERR_CTR_RB_HI                                   0x0950,0,8
#define       RS_CORR_PKT_ERR_CTR_RB_LO                                   0x0954,0,16
#define       RS_UNCORR_PKT_ERR_CTR_RB_HI                                 0x0958,0,8
#define       RS_UNCORR_PKT_ERR_CTR_RB_LO                                 0x095C,0,16
#define       XPTO_FIFO_BYP                                               0x0968,4,1
#define       XPTO_FIFO_RST                                               0x0968,5,1
#define       XPT_TS_MODE                                                 0x096C,0,1
#define       XPTO_VALID_POLARITY                                         0x096C,2,1
#define       XPTO_SYNC_POLARITY                                          0x096C,3,1
#define       XPT_DELAY_SEL_MDAT_6                                        0x097C,4,4
#define       XPT_DELAY_SEL_MPVAL_6                                       0x097C,8,4
#define       XPT_DELAY_SEL_MPSYNC_6                                      0x097C,12,4
#define       XPTO_CLOCK_EXTEND                                           0x0984,8,8
#define       XPTO_CLK_POLARITY                                           0x0988,0,8
#define       TOPAD_XTAL_CLK_INV                                          0x0988,8,1
#define       DMD0_INT_RESET                                              0x1800,0,16
#define       DMD0_QAM_TYPE                                               0x1804,0,3
#define       DMD0_MASK_TUNER_DONE                                        0x1804,3,1
#define       DMD0_QAM_ANNEX_TYPE                                         0x1804,10,1
#define       DMD0_QAM_BURST_FREEZE_ENABLE                                0x1808,13,1
#define       DMD0_QAM_BURST_FREEZE_MODE                                  0x1808,14,1
#define       DMD0_QAM_WATCHDOG_ENABLE                                    0x1814,12,1
#define       DMD0_QAM_AUTO_DETECT_ANNEX_A_MODE                           0x1814,14,1
#define       DMD0_QAM_AUTO_DETECT_ENABLE                                 0x1814,15,1
#define       DMD0_SOFTDEC_VALUE                                          0x1818,0,10
#define       DMD0_QAM_LOCK                                               0x1838,0,1
#define       DMD0_OC_DIFF_MODE                                           0x183C,0,1
#define       DMD0_EQU_FREQ_SWEEP_LIMIT                                   0x1884,4,4
#define       DMD0_EQU_FAGC_ENABLE                                        0x1884,14,1
#define       DMD0_EQU_FFE_TAP_LEAD_POSITION                              0x1898,8,2
#define       DMD0_EQU_CARR_DD_KP                                         0x18A0,5,5
#define       DMD0_EQU_SPUR_BYPASS                                        0x18BC,9,1
#define       DMD0_EQU_LLP_ENABLE                                         0x18D4,0,1
#define       DMD0_EQU_DEBUG_MSE_CALC_COEF                                0x18D8,11,5
#define       DMD0_EXTENDED_SPACE_ADDRESS                                 0x18F8,0,8
#define       DMD0_EXTENDED_SPACE_ADDRESS_AUTO_INCREMENT                  0x18F8,8,1
#define       DMD0_EXTENDED_SPACE_DATA                                    0x18FC,0,16
#define       DMD0_RESAMP_REGISTERS_BANK                                  0x1900,0,3
#define       DMD0_ACI_CUSTOM_COEF_ENABLE                                 0x1900,13,1
#define       DMD0_MF_CUSTOM_COEF_ENABLE                                  0x1900,14,1
#define       DMD0_RESAMP_RATE_RATIO_HIGH                                 0x1908,0,11
#define       DMD0_RESAMP_RATE_RATIO_LOW                                  0x190C,0,16
#define       DMD0_MF_COEF_ADDRESS                                        0x1918,0,6
#define       DMD0_AUTO_INCREMENT_MF                                      0x1918,15,1
#define       DMD0_MF_COEF_DATA                                           0x191C,0,13
#define       DMD0_GODARD_ACC                                             0x192C,0,16
#define       DMD0_MAX_FREEZE_WIN_LEN                                     0x198C,0,11
#define       DMD0_CLK_INV                                                0x1A40,0,1
#define       DMD0_FECB_TR_SYNC                                           0x1A8C,1,1
#define       DMD0_FECB_INT_D                                             0x1A8C,3,4
#define       DMD0_FECA_SRS_EN                                            0x1A80,11,1
#define       DMD0_FECA_STAMP                                             0x1A90,0,16
#define       DMD0_FECA_FRCNT                                             0x1A9C,0,16
#define       DMD0_FECA_MEF                                               0x1AA0,0,16
#define       DMD0_FECA_NCBH                                              0x1AA4,0,8
#define       DMD0_FECA_NCBL                                              0x1AA8,0,16
#define       DMD0_FECA_MCNSSD_SEL                                        0x1AB4,0,3
#define       DMD0_FECA_MCNSSD                                            0x1AB8,0,16
#define       DMD0_VALID_ACTIVE_LEVEL                                     0x1BC8,0,1
#define       DMD0_SYNC_ACTIVE_LEVEL                                      0x1BC8,1,1
#define       DMD0_MSB_LSB_FIRST                                          0x1BC8,2,1
#define       DMD0_SYNC_PULSE_WIDTH                                       0x1BC8,3,1
#define       DMD0_DISABLE_FIFO_READ_LIMIT                                0x1BC8,7,1
#define       DMD0_MPEG_FRAME_ERROR_INDICATION                            0x1BC8,8,1
#define       DMD0_BITWIZE_ENABLE_MASK                                    0x1BCC,15,1
#define       DMD0_RESTART                                                0x1BFC,0,16
#define       DIG_ANA_ASIC_RDY                                            0x6000,0,1
#define       DIG_ANA_ADC_BBCLK_ENA                                       0x6000,9,1
#define       DIG_ANA_ADC_BBCLK_RSTB                                      0x6000,10,1
#define       DIG_ANA_ADC_IFCLK_ENA                                       0x6000,11,1
#define       DIG_ANA_ADC_IFCLK_RSTB                                      0x6000,12,1
#define       DIG_ANA_ADC_NBCLK_ENA                                       0x6000,13,1
#define       DIG_ANA_ADC_REG_FE_AMP                                      0x6004,0,3
#define       DIG_ANA_ADC_REG_FE_ENA                                      0x6004,7,1
#define       DIG_ANA_ADC_SPARE                                           0x6008,8,8
#define       DIG_ANA_ADC_RTUNE                                           0x600C,4,4
#define       DIG_ANA_RFFE_RCTUNE                                         0x6010,2,4
#define       DIG_ANA_RFFE_DACIN_ENA                                      0x6018,0,1
#define       DIG_ANA_RFFE_BUF1_ENA                                       0x6018,11,1
#define       DIG_ANA_RFFE_NB_BUF_ENA                                     0x601C,8,1
#define       DIG_ANA_RFFE_LP_ENA                                         0x601C,12,1
#define       DIG_ANA_RFFE_NB_ENA                                         0x601C,13,1
#define       DIG_ANA_RFFE_LNA_TILT_MODE_SOURCE                           0x601C,14,1
#define       DIG_ANA_RFFE_INPUTMATCH                                     0x6014,4,2
#define       DIG_ANA_XTAL_CAL_START                                      0x6020,2,1
#define       DIG_ANA_XTAL_BUF_LP                                         0x6020,4,1
#define       DIG_ANA_XTAL_CAP                                            0x6024,0,5
#define       DIG_ANA_XTAL_BYP_CAL                                        0x6024,5,1
#define       DIG_ANA_XTAL_EXT_BIAS                                       0x6024,8,5
#define       DIG_ANA_XTAL_FORCE_CALDONE                                  0x6024,13,1
#define       DIG_ANA_XTAL_SPARE                                          0x602C,0,16
#define       DIG_ANA_XTAL_UPDATE                                         0x6030,2,1
#define       DIG_ANA_SERDES0_CLK_ENA                                     0x6030,3,1
#define       DIG_ANA_SERDES1_CLK_ENA                                     0x6030,4,1
#define       DIG_ANA_CLKOUT_ENA                                          0x6030,5,1
#define       DIG_ANA_CLKOUT_AMP                                          0x6030,8,5
#define       DIG_ANA_CLKOUT_TEST_MODE                                    0x6038,6,2
#define       DIG_ANA_RCTUNE_ENA                                          0x6038,8,1
#define       DIG_ANA_MISC_SPARE                                          0x603C,0,4
#define       DIG_ANA_TEST0_ADDR                                          0x6040,0,4
#define       DIG_ANA_TEST0_MODE                                          0x6040,4,4
#define       DIG_ANA_REFSX_START_TUNE                                    0x6044,12,1
#define       DIG_ANA_REFSX_SX_REG_AMP                                    0x6048,0,3
#define       DIG_ANA_REFSX_TEMP_INFO                                     0x604C,0,3
#define       DIG_ANA_REFSX_SX_REG_ENA                                    0x6054,1,1
#define       DIG_ANA_REFSX_INTMOD                                        0x6064,0,8
#define       DIG_ANA_REFSX_EN_RCTUNECLK                                  0x6064,11,1
#define       DIG_ANA_REFSX_ENA                                           0x6068,15,1
#define       DIG_ANA_RFSX_SX_REG_AMP                                     0x607C,8,3
#define       DIG_ANA_RFSX_VCO_REG_AMP                                    0x608C,0,3
#define       DIG_ANA_RFSX_SEL_DSM_ORDER3                                 0x608C,13,1
#define       DIG_ANA_IF_DAC_ENA                                          0x60C4,7,1
#define       DIG_ANA_IF_GAIN                                             0x60C8,0,6
#define       DIG_ANA_IF_RCTUNE                                           0x60C8,12,4
#define       DIG_ANA_IF_REG_ANA_AMP                                      0x60CC,0,3
#define       DIG_ANA_IF_REG_CLK_AMP                                      0x60CC,4,3
#define       DIG_ANA_IF_REG_DIG_AMP                                      0x60CC,8,3
#define       DIG_ANA_IF_SPARE                                            0x60D0,8,8
#define       DIG_ANA_TX_ENA                                              0x60D4,1,1
#define       DIG_ANA_TX_RSTB                                             0x60D4,2,1
#define       DIG_ANA_TX_CLK_FLIP                                         0x60D4,3,1
#define       DIG_ANA_TX_CLK_ENA                                          0x60D4,4,1
#define       DIG_ANA_TX_GAIN                                             0x60D4,8,3
#define       DIG_ANA_TX_SPARE                                            0x60D8,0,8
#define       ANA_DIG_XTAL_AMP_RB                                         0x60E0,0,6
#define       ANA_DIG_XTAL_CALDONE_RB                                     0x60E0,6,1
#define       ANA_DIG_XTAL_AMP_LIN_RB                                     0x60E0,8,2
#define       ANA_DIG_RCTUNE                                              0x60E0,10,4
#define       ANA_DIG_TSENS_READBACK                                      0x60E4,0,3
#define       ANA_DIG_SOC_ID                                              0x60E4,8,8
#define       ANA_DIG_SOC_FLVR                                            0x60E8,8,8
#define       ANA_DIG_REFSX_TUNE_DONE                                     0x6100,3,1
#define       ANA_DIG_RFSX_SPARE                                          0x6118,0,8
#define       DIG_ANA_TEMPSEN_ENA                                         0x611C,0,1
#define       DIG_ANA_TEMPSEN_START                                       0x611C,1,1
#define       DIG_ANA_TEMPSEN_MODE                                        0x611C,8,7
#define       DIG_ANA_TEMPSEN_DURATION                                    0x6120,0,2
#define       ANA_DIG_TEMPSEN_READY                                       0x6124,0,1
#define       ANA_DIG_TEMPSEN_OUT                                         0x6128,0,14
#define       XPT_INDIRC_ADDR_L                                           0x7800,0,16
#define       XPT_INDIRC_ADDR_M                                           0x7804,0,4
#define       XPT_INDIRC_DATA_L                                           0x780C,0,16
#define       XPT_INDIRC_DATA_M                                           0x7810,0,16
#define       XPT_PARALLEL_FIFO_RST_N                                     0x7814,7,1
#define       SERDES0_REG_MODEA_MODE                                      0x6800,0,1
#define       SERDES0_REG_MODEA_HALF_MODE_INT                             0x6800,1,1
#define       SERDES0_REG_MODEA_HALF_MODE_MASTER_AS_ODD                   0x6800,2,1
#define       SERDES0_REG_MODEA_HALF_MODE                                 0x6800,3,1
#define       SERDES0_REG_DS_DOUT_SEL                                     0x6840,0,2
#define       SERDES0_REG_DS_FRAMER_MODE_CISCO                            0x6840,4,3
#define       SERDES0_REG_DS_FRAMER_CLEAR_INT                             0x6840,8,1
#define       SERDES0_REG_DS_RS_USE_CRC                                   0x6844,4,1
#define       SERDES0_REG_DS_SCRAM_ENAB                                   0x6848,0,1
#define       SERDES0_REG_DS_SCRAM_SELF_SYNC                              0x6848,4,1
#define       SERDES0_REG_DS_LSB_FIRST_OUT                                0x6850,0,1
#define       SERDES0_REG_DS_PRBS_MODEA_SEL                               0x6860,0,2
#define       SERDES0_REG_DS_PRBS_MODEA_RST                               0x6860,4,1
#define       SERDES0_REG_NB0_SEL                                         0x6880,0,5
#define       SERDES0_REG_US_OUT_EN_INT                                   0x68C0,0,1
#define       SERDES0_REG_US_IN_EN_INT                                    0x68C0,1,1
#define       SERDES0_REG_US_LSB_FIRST_IN                                 0x68C0,8,1
#define       SERDES0_REG_US_DEFRAME_CLEAR                                0x68C4,0,1
#define       SERDES0_REG_US_SCRAM_ENAB                                   0x68C8,0,1
#define       SERDES0_REG_US_SCRAM_SELF_SYNC                              0x68C8,4,1
#define       SERDES0_REG_US_DISABLE_CORRECTION                           0x68CC,0,1
#define       SERDES0_REG_US_PRBS_MODEA_SEL                               0x68D0,0,2
#define       SERDES0_REG_US_PRBS_MODEA_RST                               0x68D0,4,1
#define       SERDES0_REG_US_PRBS_RX_CLR                                  0x68D0,12,1
#define       SERDES0_REG_US_RS_CLEAR_CNT                                 0x68D4,4,1
#define       SERDES0_REG_US_RS_USE_CRC                                   0x68D4,8,1
#define       SERDES0_REG_US_LOCKLOST_CNT_CLR                             0x68D8,4,1
#define       SERDES0_US2APB_LOCKED                                       0x68DC,0,1
#define       SERDES0_US_LOCKLOST_CNT                                     0x68DC,8,8
#define       SERDES0_REG_US_MODEA_SYNC_NUM                               0x68E0,0,6
#define       SERDES0_REG_US_MODEA_SYNC_NOT_DET_NUM                       0x68E0,6,4
#define       SERDES0_REG_US_MODEA_SYNCLOST_RANGE_NUM                     0x68E0,10,6
#define       SERDES0_REG_US_SYNCLOST_CNT_CLR                             0x68E4,4,1
#define       SERDES0_US2APB_SYNC                                         0x68E8,0,1
#define       SERDES0_US_SYNCLOST_CNT                                     0x68E8,8,8
#define       SERDES0_US_PRBS_RX_ERR_LSB                                  0x68F0,0,16
#define       SERDES0_US_PRBS_RX_ERR_MSB                                  0x68F4,0,8
#define       SERDES0_CORRECTED_PACKETS_LSB                               0x68F8,0,16
#define       SERDES0_CORRECTED_PACKETS_MSB                               0x68FC,0,16
#define       SERDES0_UNCORRECTED_PACKETS_LSB                             0x6900,0,16
#define       SERDES0_UNCORRECTED_PACKETS_MSB                             0x6904,0,16
#define       SERDES0_TOTAL_PACKETS_LSB                                   0x6910,0,16
#define       SERDES0_TOTAL_PACKETS_MSB                                   0x6914,0,16
#define       SERDES0_US_PRBS_MODEA_ERR_CNT_LSB                           0x6928,0,16
#define       SERDES0_US_PRBS_MODEA_ERR_CNT_MSB                           0x692C,0,16
#define       SERDES0_REG_PHY_REF_SSP_EN                                  0x6A00,12,1
#define       SERDES0_REG_PHY_MPLL_MULTIPLIER                             0x6A04,0,7
#define       SERDES0_REG_PHY_TEST_POWERDOWN                              0x6A08,8,1
#define       SERDES0_REG_PHY_RESET_ALL                                   0x6A0C,0,1
#define       SERDES0_REG_PHY_BPR_RESET                                   0x6A0C,4,1
#define       SERDES0_REG_PHY_RX0_ALIGN_EN                                0x6A0C,12,1
#define       SERDES0_REG_PHY_RX_INVERT                                   0x6A40,0,1
#define       SERDES0_REG_PHY_RX_EQ                                       0x6A44,0,3
#define       SERDES0_REG_PHY_TX_INVERT                                   0x6A80,0,1
#define       SERDES0_REG_PHY_TX_AMPLITUDE_GEN3                           0x6A84,0,7
#define       SERDES0_REG_PHY_TX_PREEMPH_GEN3                             0x6A84,8,6
#define       SERDES0_PHY_STATUS_READY                                    0x6AC0,0,1
#define       SERDES1_REG_DS_FRAMER_MODE_CISCO                            0x7040,4,3
#define       SERDES1_US2APB_LOCKED                                       0x70DC,0,1
#define       SERDES1_US_LOCKLOST_CNT                                     0x70DC,8,8
#define       SERDES1_REG_US_MODEA_SYNC_NUM                               0x70E0,0,6
#define       SERDES1_US_PRBS_RX_ERR_LSB                                  0x70F0,0,16
#define       SERDES1_US_PRBS_RX_ERR_MSB                                  0x70F4,0,8
#define       SERDES1_CORRECTED_PACKETS_LSB                               0x70F8,0,16
#define       SERDES1_CORRECTED_PACKETS_MSB                               0x70FC,0,16
#define       SERDES1_UNCORRECTED_PACKETS_LSB                             0x7100,0,16
#define       SERDES1_UNCORRECTED_PACKETS_MSB                             0x7104,0,16
#define       SERDES1_TOTAL_PACKETS_LSB                                   0x7110,0,16
#define       SERDES1_TOTAL_PACKETS_MSB                                   0x7114,0,16
#define       SERDES1_US_PRBS_MODEA_ERR_CNT_LSB                           0x7128,0,16
#define       SERDES1_US_PRBS_MODEA_ERR_CNT_MSB                           0x712C,0,16
#define       SERDES1_PHY_STATUS_READY                                    0x72C0,0,1
#define       ADC_DC_OFFSET_BYP                                           0x800C,0,1
#define       ADC_CAL_ADDR                                                0x8018,0,16
#define       ADC_CAL_WDATA                                               0x801C,0,16
#define       ADC_CAL_WSTB                                                0x8020,0,1
#define       ADC_CAL_RDATA                                               0x8024,0,16
#define       ADC_CAL_FREEZE_GAIN_MISMATCH_RB                             0x8028,3,1
#define       ADC_CAL_FREEZE_DC_OFFSET_RB                                 0x8028,4,1
#define       PHY_RTL_VERSION                                             0x87FC,0,16
#define       DFE_ADC_IF_EN                                               0x983C,10,1
#define       DFE_WBCLK_EN                                                0x9858,9,1
#define       DFE_UPX_CLK_EN                                              0x9858,11,1
#define       DFE_WBCLK_RESET                                             0x9858,14,1
#define       DFE_UPX_RESET                                               0x9858,15,1
#define       DFE_CLR_DP_NBAND                                            0x9860,0,12
#define       DFE_IFDAC_IF_EN                                             0x9864,7,1
#define       DFE_TXDAC_IF_EN                                             0x9864,8,1
#define       DFE_NB15_XBAR_SEL                                           0x9864,10,2
#define       DFE_NB04_XBAR_SEL                                           0x9864,12,2
#define       DFE_USRESAMP_CLK_EN                                         0x9864,15,1
#define       DFE_USRESAMP_RESET                                          0x9868,0,1
#define       DFE_UPX_DDFS_MODE                                           0x9868,1,1
#define       DFE_UPX_DDFS_CLK_FREQ                                       0x9868,2,2
#define       DFE_UPX_DDFS0_FREQ_HI                                       0x986C,0,1
#define       DFE_UPX_DDFS0_FREQ_LO                                       0x9870,0,16
#define       DFE_UPX_DDFS1_FREQ_HI                                       0x9878,0,1
#define       DFE_UPX_DDFS1_FREQ_LO                                       0x987C,0,16
#define       DFE_UPX_DDFS2_FREQ_HI                                       0x9884,0,1
#define       DFE_UPX_DDFS2_FREQ_LO                                       0x9888,0,16
#define       DFE_UPX_DDFS3_FREQ_HI                                       0x988C,0,1
#define       DFE_UPX_DDFS3_FREQ_LO                                       0x9890,0,16
#define       DFE_UPX_GAIN                                                0x9894,0,3
#define       DFE_UPX_BR0_EN                                              0x9894,3,1
#define       DFE_UPX_SINX_COEFF0                                         0x9898,0,9
#define       DFE_UPX_SINX_COEFF1                                         0x989C,0,9
#define       DFE_UPX_SINX_COEFF2                                         0x98A0,0,9
#define       DFE_TX_RESAMP_DOUT_EN                                       0x98A0,9,1
#define       DFE_TX_RESAMP_OP_EN                                         0x98A0,10,1
#define       DFE_TX_RESAMP_RATE                                          0x98A0,11,1
#define       DFE_CHN0_XBAR_SEL                                           0xA000,0,4
#define       DFE_CHN0_DMIX_FCW_HI                                        0xA004,0,1
#define       DFE_CHN0_DMIX_FCW_LO                                        0xA008,0,16
#define       DFE_CHN0_ENA                                                0xA01C,8,1
#define       DFE_CHN0_CSF_COEFF0                                         0xA020,0,15
#define       DFE_CHN0_DAGC_SETPT                                         0xA06C,0,10
#define       DFE_CHN0_VRI_DOWNSAMP_RATE_HI                               0xA090,0,7
#define       DFE_CHN0_VRI_DOWNSAMP_RATE_LO                               0xA094,0,16
#define       DFE_CHN1_DAGC_SETPT                                         0xA26C,0,10
#define       DFE_CHN2_DAGC_SETPT                                         0xA46C,0,10
#define       DFE_CHN3_DAGC_SETPT                                         0xA66C,0,10
#define       ENABLE_INPUT0                                               0x30000,0,1
#define       ENABLE_INPUT1                                               0x30000,1,1
#define       ENABLE_INPUT2                                               0x30000,2,1
#define       ENABLE_INPUT3                                               0x30000,3,1
#define       ENABLE_INPUT4                                               0x30000,4,1
#define       ENABLE_INPUT5                                               0x30000,5,1
#define       ENABLE_INPUT6                                               0x30000,6,1
#define       ENABLE_INPUT7                                               0x30000,7,1
#define       STREAM_MUXMODE0                                             0x30008,0,2
#define       STREAM_MUXMODE1                                             0x30008,2,2
#define       LSB_FIRST0                                                  0x3000C,16,1
#define       LSB_FIRST1                                                  0x3000C,17,1
#define       LSB_FIRST2                                                  0x3000C,18,1
#define       LSB_FIRST3                                                  0x3000C,19,1
#define       LSB_FIRST4                                                  0x3000C,20,1
#define       LSB_FIRST5                                                  0x3000C,21,1
#define       LSB_FIRST6                                                  0x3000C,22,1
#define       LSB_FIRST7                                                  0x3000C,23,1
#define       SYNC_FULL_BYTE0                                             0x30010,0,1
#define       SYNC_FULL_BYTE1                                             0x30010,1,1
#define       SYNC_FULL_BYTE2                                             0x30010,2,1
#define       SYNC_FULL_BYTE3                                             0x30010,3,1
#define       SYNC_FULL_BYTE4                                             0x30010,4,1
#define       SYNC_FULL_BYTE5                                             0x30010,5,1
#define       SYNC_FULL_BYTE6                                             0x30010,6,1
#define       SYNC_FULL_BYTE7                                             0x30010,7,1
#define       SYNC_POLARITY0                                              0x30010,8,1
#define       SYNC_POLARITY1                                              0x30010,9,1
#define       SYNC_POLARITY2                                              0x30010,10,1
#define       SYNC_POLARITY3                                              0x30010,11,1
#define       SYNC_POLARITY4                                              0x30010,12,1
#define       SYNC_POLARITY5                                              0x30010,13,1
#define       SYNC_POLARITY6                                              0x30010,14,1
#define       SYNC_POLARITY7                                              0x30010,15,1
#define       VALID_POLARITY1                                             0x30014,1,1
#define       VALID_POLARITY2                                             0x30014,2,1
#define       VALID_POLARITY3                                             0x30014,3,1
#define       VALID_POLARITY4                                             0x30014,4,1
#define       VALID_POLARITY5                                             0x30014,5,1
#define       VALID_POLARITY6                                             0x30014,6,1
#define       VALID_POLARITY7                                             0x30014,7,1
#define       CLOCK_POLARITY0                                             0x30010,16,1
#define       CLOCK_POLARITY1                                             0x30010,17,1
#define       CLOCK_POLARITY2                                             0x30010,18,1
#define       CLOCK_POLARITY3                                             0x30010,19,1
#define       CLOCK_POLARITY4                                             0x30010,20,1
#define       CLOCK_POLARITY5                                             0x30010,21,1
#define       CLOCK_POLARITY6                                             0x30010,22,1
#define       CLOCK_POLARITY7                                             0x30010,23,1
#define       ENABLE_PARALLEL_OUTPUT                                      0x30010,27,1
#define       VALID_POLARITY0                                             0x30014,0,1
#define       NCO_COUNT_MIN0                                              0x30044,16,8
#define       PID_CONTEXT_SELECT0                                         0x30190,0,1
#define       PID_CONTEXT_SELECT1                                         0x301B0,0,1
#define       TS_CLK_OUT_EN0                                              0x301D4,0,1
#define       TS_CLK_OUT_EN_PARALLEL                                      0x301D4,8,1
#define       NCO_COUNT_MIN1                                              0x30238,0,8
#define       NCO_COUNT_MIN2                                              0x30238,8,8
#define       NCO_COUNT_MIN3                                              0x30238,16,8
#define       NCO_COUNT_MIN4                                              0x30238,24,8
#define       NCO_COUNT_MIN5                                              0x3023C,0,8
#define       NCO_COUNT_MIN6                                              0x3023C,8,8
#define       NCO_COUNT_MIN7                                              0x3023C,16,8
#define       PID_VALID0                                                  0x38000,0,1
#define       PID_DROP0                                                   0x38000,1,1
#define       PID_REMAP0                                                  0x38000,2,1
#define       PID_VALUE0                                                  0x38000,4,13
#define       PID_MASK0                                                   0x38000,19,13
#define       PID_REMAP_VALUE0                                            0x38004,0,13
#define       PID_PORT_ID0                                                0x38004,16,3
#define       KNOWN_PID_VALID0                                            0x39000,0,1
#define       KNOWN_PID_DROP0                                             0x39000,1,1
#define       KNOWN_PID_REMAP0                                            0x39000,2,1
#define       KNOWN_PID_REMAP_VALUE0                                      0x39000,16,13
#define       PID_VALID1                                                  0x3A000,0,1
#define       KNOWN_PID_VALID1                                            0x3B000,0,1

//HYDRA_XPT
#define       ENABLE_OUTPUT0                                              0x3000C,0,1
#define       ENABLE_OUTPUT1                                              0x3000C,1,1
#define       ENABLE_OUTPUT2                                              0x3000C,2,1
#define       ENABLE_OUTPUT3                                              0x3000C,3,1
#define       ENABLE_OUTPUT4                                              0x3000C,4,1
#define       ENABLE_OUTPUT5                                              0x3000C,5,1
#define       ENABLE_OUTPUT6                                              0x3000C,6,1
#define       ENABLE_OUTPUT7                                              0x3000C,7,1
#define       KNOWN_CONTEXT_REG_SELECT0                                   0x30190,1,1
#define       PID_MUX_SELECT0                                             0x30190,4,4
#define       KNOWN_PID_MUX_SELECT0                                       0x30190,8,4
#define       PID_DEFAULT_DROP0                                           0x30190,12,1
#define       KNOWN_CONTEXT_REG_SELECT1                                   0x301B0,1,1
#define       PID_MUX_SELECT1                                             0x301B0,4,4
#define       KNOWN_PID_MUX_SELECT1                                       0x301B0,8,4
#define       PID_DEFAULT_DROP4                                           0x301B0,12,1
#define       APPEND_BYTES0                                               0x30008,4,2
#define       APPEND_BYTES1                                               0x30008,6,2
#define       INP0_MERGE_HDR0                                             0x30058,0,32
#define       MODE_27MHZ                                                  0x30184,0,1
